package fpga_generation.java_base;

public class base_mm_slave extends base_component
{
	private base_interface_mm slave_port;
	private int bitwidth;
	private boolean explicitDataWidth;
	private String interfaceName;
	
	public base_mm_slave(String name, String interfaceName)
	{
		super(name);
		this.interfaceName = interfaceName;
		explicitDataWidth = false;
	}
	
	public String getName() {
		return name;
	}
	
	public String getInterface() {
		return name + "." + this.interfaceName;
	}
	
	public void connect(base_mm_master master)
	{
		if (!explicitDataWidth) {
			bitwidth = master.bitwidth;
		}
	}
	
	
	public void setDataWidth(int bits) 
	{
		explicitDataWidth = true;
		bitwidth = bits;
	}
	
}